1. Field of the Invention
The present invention relates to a multi-layered wiring structure of a highly integrated semiconductor device, and a manufacturing method thereof.
2. Description of the Related Art
Remarkable developments have been made to high concentration and integration of a semiconductor device, such as an IC or an LSI, and as a result, a multi-layered structure is often used as a wiring structure for such a device. In this structure in which wirings are multi-layered, the area of the wirings is reduced to prevent the size of the chip from being enlarged, the length of the wirings is shortened thereby to restrain delays in the operation speed, which are caused by the resistance of the wirings, and arrangement of the wirings is automatized.
In the following, the multi-layered wiring structure and the manufacturing method thereof, which are applied to a conventional semiconductor device will be explained with reference to a two-layered Al wiring structure cited as an example. FIG. 1 is a sectional view showing a multi-layered structure realized on a semiconductor substrate. A lower wiring 2 made of Al or the like is formed on a silicon semiconductor substrate 10, with an insulating film 1 made of SiO.sub.2 or the like being inserted between the wiring and the substrate. The lower wiring 2 is covered with an insulating film 3 made of SiO.sub.2 or other material. The surface of this insulating film may be flattened, if necessary, when upper wirings must further be formed on this insulating film. A conventional technique, such as a glass-flow method, an etch-back method, or the like, is used for flattening the film. Thereafter, a contact hole 9 is formed in the lower insulating film 3 by photolithography and etching. An Al film is then deposited on the lower insulating film 3 and in the contact hole 9, by a sputtering method or the like, and the Al film is subjected to patterning, thereby to form an upper wiring 4. Then, an upper insulating film 5 made of PSG or CVD SiO.sub.2 is deposited on the wiring 4 (see FIG. 1A). In the case of a two-layered wiring structure, the upper insulating film 5 serves as a protective insulating film. If upper layers are deposited on the film 5, it serves as an inter-layer insulating film. In this case, a contact hole is further formed in the upper insulating film 5 on which a third wiring is formed. Fourth and fifth wirings may further be formed thereon, with insulating films being layered on respective wirings.
Another method may be as follows. A contact hole is formed in the lower insulating film 3, such that the lower wiring 2 is exposed to the contact hole. Then, tungsten which grows to be a connection wiring 7 is selectively grown in the contact hole, and then, an Al film is deposited on the lower insulating film 3, and is subjected to patterning, thereby to form an upper wiring 4. An upper insulating film 5 is made of CVF SiO.sub.2 or the like is further provided on the upper wiring 4 (see FIG. 1B). In the case of forming further wirings thereon, a contact hole must be formed every time an inter-layer insulating film is additionally formed, and a connection wiring must also be deposited in the hole, as in the above example.
As the other conventional method in which a contact hole is formed, there is a method of electrically connecting a gate electrode and an upper wiring in the case where the lower wiring is a gate electrode (see Published Unexamined Japanese Patent Application No. 63-127551). In this method, contact hole is formed in one single step, for each layer and film, from the upper insulating film formed on the upper wiring to the gate electrode. In this contact hole, for example, a connection wiring is provided by selective growth of tungsten (W).
In a conventional multi-layered structure, connection between layers has been obtained by the methods stated above. However, for example, in the method of forming an upper wiring by a sputtering method after having formed a contact hole as shown in FIG. 1A, Al is not uniformly filled in the contact hole, and therefore, wirings may be disconnected. This method thus causes a problem of defective wiring. This problem appears more frequently when the diameter of the contact hole is reduced to be small, and when the number of layers constituting the multi-layered wiring structure is increased, i.e., when a so-called aspect ratio (depth d/width w) for the shape of the contact hole is increased. In addition, in the method of using a connection wiring formed by the selective growth as shown in FIG. 1B, the surface of tungsten must be processed with Ar ions, in order to achieve a good contact between Al and tungsten, when tungsten which constitutes a connection wiring in the contact hole is subjected to selective growth, and an Al film is then formed which serves as an upper wiring. In this case, a gate oxide film of a transistor which constitutes the semiconductor device may be broken due to irradiation of Ar ions. In another conventional method explained above, in which a contact hole is formed by one single step from the upper insulating to the gate oxide film, the upper and lower wirings are gradually connected as the selective growth of tungsten proceeds. This method therefore does not involve the above problem, but includes the following problem. This method is explained in FIG. 2 which is a partial sectional view showing the semiconductor substrate of a semiconductor device. When forming a contact hole 9, the upper insulating film 5, upper wiring 4, and the lower insulating film 3 are etched to expose the surface of the lower wiring 2. Connection wirings 7 and 71 made of tungsten are prepared by selective growth in the contact hole 9. In this step, the upper wiring 4 and lower wiring 2 both exposed to the contact hole 9 serve as growth seeds, and tungsten grows up therefrom. It is however impossible to apply this method to a semiconductor device in which the aspect ratio is increased to be 1 or more as a result of high integration. Specifically, since this method uses two bases, tungsten grows up to be a cap 71 when tungsten is subjected to rapid growth at the base of the upper wiring 4, while tungsten does not sufficiently grow up at the base of the lower wiring 2. As a result, the connection wirings 7 and 71 are formed separately, and a space remains between the two separate wirings formed.
Further, the conventional methods involves a problem that, every time any two of wirings are connected with each other, the inter-layer insulating film must be etched to form a contact hole, and therefore, manufacturing steps must be increased.
The present invention has as its object to provide a method of manufacturing a semiconductor device which is excellent in electric characteristics and is suitable for high integration, and to provide a semiconductor device having a multi-layered wiring structure which can easily be manufactured.